This invention relates to a conductive film-attached substrate which is suited for use in a thin film transistor substrate.
At present, an active matrix-driving liquid crystal display has been employed as a display for various kinds of portable machine such as a notebook type computer because of its advantageous features such as high image quality, thin configuration, light weight, low power consumption, etc. For the manufacture of this active matrix-driving liquid crystal display, a thin film transistor (TFT) is mainly employed.
In recent years, there have been proposed various attempts to improve the quality and reliability of TFT as a liquid crystal display element for the purpose of realizing at a low cost an active matrix-driving liquid crystal display of high image quality and high reliability. In particular, in order to realize improvements in quality and reliability of the active matrix-driving liquid crystal display, it is imperative to improve the quality, durability and environmental resistance of the protective insulating film of TFT. Further, in viewpoint of mass productivity, it is required that a protective insulating film of high quality and high reliability can be manufactured relatively easily and at a low cost.
Conventionally, the structure as shown in FIG. 1 is known as a substrate for TFT, which is excellent in quality and in reliability. Referring to FIG. 1, a glass substrate 1 functioning as a translucent insulating substrate is provided on its main surface with a semiconductor layer 2 formed of a polycrystalline silicon and shaped into an island. This semiconductor layer 2 is constituted by a channel region 3, a high resistance drain region 4 doped with an impurity at a controlled low concentration and disposed neighboring one side of the channel region 3, a high resistance source region 5 doped with an impurity at a controlled low concentration and disposed neighboring the other side of the channel region 3, a low resistance drain region 6 doped with an impurity at a controlled high concentration and disposed neighboring the outer side of the drain region 4, and a low resistance source region 7 doped with an impurity at a controlled high concentration and disposed neighboring the outer side of the source region 5. Since these high resistance drain region 4 and high resistance source region 5 are implanted with an impurity such as phosphorus atom or boron atom at a low concentration, the construction shown in FIG. 1 is called a lightly doped drain structure (LDD structure). Further, since the electric resistance of these high resistance drain region 4 and source region 5 is controlled at an intermediate value between that of the channel region 3 and that of the low resistance drain region 6 or of the low resistance source region 7, the LDD structure is known to enhance the reliability of TFT.
Further, the upper surface of the semiconductor layer 2 is covered with a gate insulating film 8 consisting of silicon oxide, the upper surface of which is in turn covered with a gate electrode 9 constituting a first conductive film and formed of aluminum, a molybdenum-tungsten alloy, titanium or tantalum and with a gate wiring (not shown) which is formed integral with the gate electrode 9. Furthermore, an interlayer insulating film 10 formed of silicon oxide is formed to cover the upper surfaces of gate insulating film 8 and gate electrode 9. Contact holes 11 and 12 are formed respectively passing through a portion of the gate insulating film 8 and of gate electrode 9 which is respectively disposed over the low resistance drain region 6 and the low resistance source region 7.
A pixel electrode 13 formed of ITO (indium tin oxide) is formed as an oxide conductive film on a portion of the interlayer insulating film 10.
Further, a source electrode 14 and a drain electrode 15, each formed of aluminum, molybdenum or titanium and functioning as a second conductive film, are formed on the interlayer insulating film 10. Additionally, a signal wiring (not shown) which is connected with the drain electrode 15 is formed on the interlayer insulating film 10. In this case, the source electrode 14 is connected via the contact hole 11 with the low resistance source region 7 and with the pixel electrode 13, while the drain electrode 15 is connected via the contact hole 12 with the low resistance drain region 6.
Further, a protective insulating film 16 consisting of silicon nitride is formed in such a manner that the region over the pixel electrode 13 and the region to be connected with an external electric circuit (not shown) are left open or exposed and that the regions including the interlayer insulating film 10, the source electrode 14 and the drain electrode 15 are covered by this protective insulating film 16, thus forming a thin film transistor substrate.
Next, this protective insulating film 16 will be explained in detail. This protective insulating film 16 is formed for the purpose of enhancing the characteristic of TFT, ensuring the initial performance of TFT, and assuring the high reliability and environmental resistance of TFT. Therefore, the protective insulating film 16 is required to be not only mechanically strong, but also high in dielectric strength and capable of preventing undesirable impurities such as movable ions (Na ion, K ion, etc.) or water that may markedly deteriorate the property and reliability of TFT from penetrating into TFT from the external atmosphere or during the manufacturing process thereof.
A film formed of silicon nitride is generally known to relatively sufficiently meet the aforementioned requirements. As for the method of forming a silicon nitride film, a plasma CVD method where a mixed gas mainly consisting of SiH.sub.4 (monosilane) gas and NH.sub.3 (ammonia) gas is employed as a raw material gas. In this plasma CVD method employing such a mixed gas, the temperature of substrate is required to be in the range of 200 to 450.degree. C. in order to obtain a silicon nitride film which is excellent in electric property and reliability. It is also known in this plasma CVD method that the higher the temperature is within this temperature range, the more excellent would be the resultant film.
However, when the temperature of substrate becomes 250.degree. C. or more, a silicon nitride film is caused to grow extraordinarily thus generating a hemispherical or dome-shaped projection 21 on the surface of the ITO film 13 functioning as a pixel electrode as shown in FIG. 2. Therefore, the formation of a silicon nitride film has been conventionally performed by setting the temperature of substrate to less than 250.degree. C.
Next, the extraordinary growth of the silicon nitride film 16 on the surface of the ITO film 13 and inconveniences of this extraordinary growth will be explained.
Though it may be also dependent upon the quality of an underlying layer, i.e. the ITO film 13, the temperature to generate the aforementioned extraordinary growth of silicon nitride film 16 is approximately 250.degree. C. Therefore, the aforementioned extraordinary growth of silicon nitride can be scarcely recognized if the temperature of the underlying substrate is less than 250.degree. C., but can be sharply developed when the temperature of the substrate exceeds over 250.degree. C.
The hemispherical or dome-shaped projection to be formed due to this extraordinary growth may develop up to several micrometers in diameter and about three times as large as the thickness of the normal film portion in height. Further, a void 22 may also be generated between the projections 21 as shown in FIG. 2.
The reason for generating the aforementioned extraordinary growth of silicon nitride film 16 on the surface of the ITO film 13 may be ascribed to the fact that the ion or radical originating from the hydrogen atom that has been generated as a result of the plasma decomposition of NH.sub.3 gas or SiH.sub.4 gas included in a raw material gas acts to reduce the surface of the ITO film 13 (a metal oxide film), whereby a silicon nitride film is allowed to selectively grow by making use of this locally reduced portion of the ITO film 13 as a nucleus.
If the silicon nitride film 16 is extraordinarily grown partially on the surface of the ITO film 13, a difference in etching rate is caused to generate at a subsequent patterning or etching process due to the denaturing of the extraordinarily grown portion of the silicon nitride film 16 as compared with that of the normal film portion of the silicon nitride film 16, thus preventing the silicon nitride film 16 from being uniformly etched. Depending on the film-forming conditions of silicon nitride film, the etching rate of the extraordinarily grown portion of the silicon nitride film 16 may be faster or slower than that of the normally grown portion. For example, when the etching rate of the extraordinarily grown portion is slower than that of the normally grown portion, a residual portion 23 of the silicon nitride film 16 would be generated on the surface of the ITO film 13 as shown in FIG. 3.
Further, the configuration of the etched edge portion of a silicon nitride film after the etching process may become rough as indicated by the region "A" in FIG. 3 irrespective of the etching rate. When the etched edge portion becomes rough or a residual etching portion 23 is generated as shown in FIG. 3, the orientation of liquid crystal at these portions may be disordered thereby causing the control in driving of liquid crystal to become difficult, thus deteriorating the display performance of a liquid crystal display.
Furthermore, when a silicon nitride is subjected to an etching work by making use of a chemical, the chemical may be entrapped in the void 22 and may be subsequently exuded out of the void 22 with time, thus contaminating the liquid crystal or eroding the signal wiring of a thin film transistor substrate. As a result, the display performance of the liquid crystal display may be deteriorated, or the reliability of the liquid crystal display may be badly affected.
As a countermeasure to prevent the aforementioned extraordinary growth of a silicon nitride film on the surface of an ITO film, a method has been proposed wherein the protective insulating film of thin film transistor is constituted by a laminate film comprising a silicon oxide film and a silicon nitride film. In this case, as a first protective insulating film to be directly contacted with the ITO film, a silicon oxide film is formed by making use of a plasma CVD method using a raw material gas consisting mainly of SiH.sub.4 gas and N.sub.2 O (dinitrogen monoxide) gas, and then a silicon nitride film is successively formed in the same manner as the aforementioned conventional method. Since the plasma atmosphere to be employed in the formation of a silicon oxide film is not reductive to the ITO film, there is no possibility of generating an extraordinary growth of a silicon oxide film on the surface of ITO film.
However, it is generally difficult to work a silicon oxide film and a silicon nitride film into a desired configuration by making use of a single patterning step and a single etching step. For example, when a reactive ion etching (RIE) method is employed by making use of a reaction gas mixture consisting mainly of CF.sub.4 gas (or SF.sub.6 gas) and O.sub.2 gas, the etching rate of the silicon nitride film is much higher than that of silicon oxide film, so that the side wall of the silicon nitride film may be excessively etched during the etching of silicon oxide film or shaped into a reversely tapered configuration.
On the other hand, when a wet etching method is employed by making use of a chemical consisting mainly of hydrogen fluoride, the etching rate of the silicon oxide film is much higher than that of silicon nitride film, so that the side wall of the silicon oxide film may be excessively etched, thus turning the etched side wall thereof into a configuration where the silicon nitride film is overhung.
When the patterning step or the etching step is repeated twice, the aforementioned problem of worked side wall configuration may be substantially overcome. However, the repetition of the patterning step or the etching step would lead to an increase in processing step, thereby inviting an increase in tact time and a decrease in throughput, thus giving rise to the deterioration of productivity and an increase in manufacturing cost.